1. Field of Invention
The present invention relates to a method of manufacturing and an application of a dual alignment photomask. More particularly, the present invention relates to a method of manufacturing a dual alignment photomask and a method of forming a dual damascene structure using only one dual alignment photomask.
2. Description of Related Art
Conventionally, two photolithographic operations using two different photomasks have to be conducted to form a dual damascene structure. One photomask is used for forming the metal trench lines, while the other photomask is used for forming the metal vias.
FIGS. 1A through 1F are schematic, cross-sectional views showing the progression of steps in producing a conventional dual damascene structure. First, as shown in FIG. 1A, a semiconductor substrate (not shown in the figure) is provided. The semiconductor substrate has a first inter-metal dielectric layer 12, a silicon nitride (SiN) layer 14 and a second inter-metal dielectric layer 16 formed on top. The silicon nitride layer 14 serves an etching stop layer that prevents the over-etching of material during the metal trench line etching operation.
Next, as shown in FIG. 1B, a photoresist layer 18 is formed over the second inter-metal dielectric layer 16 using a special photomask (not shown). Then, the second inter-metal dielectric layer 16 is etched to form metal trench lines 20 and 22 (shown as a U-shaped cut in the cross-sectional diagram). Thereafter, the photoresist layer 18 is removed forming a structure as shown in FIG. 1C.
As shown in FIG. 1D, another photoresist layer 24 is formed over the second inter-metal dielectric layer 16 again using another special photomask (not shown). Then, a portion of the silicon nitride layer 14 and the first inter-metal dielectric layer 12 are etched to form a via 26 within the metal trench line region 20. Subsequently, metal is deposited, filling the via 26 and the metal trench lines 20 and 22, to form a metallic layer 28 as shown in FIG. 1E. Finally, excess metal above the second inter-metal dielectric layer 16 is removed using, for example, a chemical-mechanical polishing (CMP) method. The remaining portions of metallic layer 28a have a planar upper surface as shown in FIG. 1F.
In the aforementioned operation, the dual damascene structure requires two etching operations using two different photomasks. This not only increases the production cost, but also increases incidence of mask misalignment. Any mask misalignment contributes to processing errors that may ultimately lower the reliability of devices.
Furthermore, although using the silicon nitride layer as an etching stop layer is able to prevent over-etching, the deposition of a silicon nitride layer on top of an inter-metal dielectric layer can lead to additional film compression stresses. Together with film tensile stresses produced by the silicon dioxide of the inter-metal dielectric layer, these stresses are capable of producing cracks or discontinuity along the sidewalls of the vias. In addition, the silicon nitride layer can affect the ultimate width of the via after an etching operation, and hence may lead to variation and instability of device resistance.
In light of the foregoing, there is a need to reduce the number of mask-making operations as well as to improve the processing steps needed to carry out for forming the dual damascene structure.